gpio_config_reg2
Specifies the bit width of port A.
| Module Instance | Base Address | Register Address |
|---|---|---|
| gpio0 | 0xFF708000 | 0xFF708070 |
| gpio1 | 0xFF709000 | 0xFF709070 |
| gpio2 | 0xFF70A000 | 0xFF70A070 |
Offset: 0x70
Access: RO
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
encoded_id_pwidth_d RO 0x7 |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
encoded_id_pwidth_d RO 0x7 |
encoded_id_pwidth_c RO 0x7 |
encoded_id_pwidth_b RO 0x7 |
encoded_id_pwidth_a RO 0x1C |
||||||||||||
gpio_config_reg2 Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 19:15 | encoded_id_pwidth_d | Specifies the width of GPIO Port D. Ignored because there is no Port D in the GPIO.
|
RO | 0x7 | ||||||
| 14:10 | encoded_id_pwidth_c | Specifies the width of GPIO Port C. Ignored because there is no Port C in the GPIO.
|
RO | 0x7 | ||||||
| 9:5 | encoded_id_pwidth_b | Specifies the width of GPIO Port B. Ignored because there is no Port B in the GPIO.
|
RO | 0x7 | ||||||
| 4:0 | encoded_id_pwidth_a | Specifies the width of GPIO Port A. The value 28 represents the 29-bit width less one.
|
RO | 0x1C |