gpio_ls_sync

The Synchronization level register is used to synchronize input with l4_mp_clk
Module Instance Base Address Register Address
gpio0 0xFF708000 0xFF708060
gpio1 0xFF709000 0xFF709060
gpio2 0xFF70A000 0xFF70A060

Offset: 0x60

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

gpio_ls_sync

RW 0x0

gpio_ls_sync Fields

Bit Name Description Access Reset
0 gpio_ls_sync

The level-sensitive interrupts is synchronized to l4_mp_clk.

Value Description
0x0 No synchronization to l4_mp_clk
0x1 Synchronize to l4_mp_clk
RW 0x0