dmasa

DMA Operation Control
Module Instance Base Address Register Address
uart0 0xFFC02000 0xFFC020A8
uart1 0xFFC03000 0xFFC030A8

Offset: 0xA8

Access: WO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

dmasa

WO 0x0

dmasa Fields

Bit Name Description Access Reset
0 dmasa

This register is used to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example, if the DMA disables the channel, then the uart should clear its request. This will cause the Tx request, Tx single, Rx request and Rx single signals to de-assert. Note that this bit is 'self-clearing' and it is not necessary to clear this bit.

WO 0x0