srr

Provides Software Resets for Tx/Rx FIFO's and the uart.
Module Instance Base Address Register Address
uart0 0xFFC02000 0xFFC02088
uart1 0xFFC03000 0xFFC03088

Offset: 0x88

Access: WO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

xfr

WO 0x0

rfr

WO 0x0

ur

WO 0x0

srr Fields

Bit Name Description Access Reset
2 xfr

This is a shadow register forthe Tx FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO.This resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA Tx request and single signals.

Value Description
0x0 No reset Tx FIFO
0x1 Reset Tx FIFO
WO 0x0
1 rfr

This is a shadow register for the Rx FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the receive FIFO. This resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA Rx request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear this bit.

Value Description
0x0 No reset Rx FIFO
0x1 Reset Rx FIFO
WO 0x0
0 ur

This asynchronously resets the UART and synchronously removes the reset assertion.

Value Description
0x0 No reset Uart
0x1 Reset Uart
WO 0x0