tfr

Used in FIFO Access test mode.

Module Instance	Base Address	Register Address
`uart0`	`0xFFC02000`	`0xFFC02074`
`uart1`	`0xFFC03000`	`0xFFC03074`

Offset: 0x74

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`tfr` `RO 0x0`

tfr Fields

Bit	Name	Description	Access	Reset
7:0	`tfr`	These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are enabled, reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the transmit FIFO and gives the next data value that is currently at the top of the FIFO. When FIFO's are not enabled, reading this register gives the data in the THR.	`RO`	`0x0`