mcr

Reports various operations of the modem signals
Module Instance Base Address Register Address
uart0 0xFFC02000 0xFFC02010
uart1 0xFFC03000 0xFFC03010

Offset: 0x10

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

afce

RW 0x0

loopback

RW 0x0

out2

RW 0x0

out1

RW 0x0

rts

RW 0x0

dtr

RW 0x0

mcr Fields

Bit Name Description Access Reset
5 afce

When FIFOs are enabled, the Auto Flow Control enable bits are active.

Value Description
0x0 Auto Flow Control Mode disabled
0x1 Auto Flow Control Mode enabled
RW 0x0
4 loopback

This is used to put the UART into a diagnostic mode for test purposes. If UART mode is NOT active, bit [6] of the modem control register MCR is set to zero, data on the sout line is held high, while serial data output is looped back to the sin line, internally. In this mode all the interrupts are fully functional. Also, in loopback mode, the modem control inputs (uart_dsr_n, uart_cts_n, uart_ri_n, uart_dcd_n) are disconnected and the modem control outputs (uart_dtr_n, uart_rts_n, uart_out1_n, uart_out2_n) are loopedback to the inputs, internally.

 RW 0x0
3 out2

This is used to directly control the user-designated uart_out2_n output. The value written to this location is inverted and driven out on uart_out2_n Note: In Loopback mode bit 4 of the modem control register (MCR) is set to one, the uart_out2_n output is held inactive high while the value of this location is internally looped back to an input.

Value Description
0x0 uart_out2_n de-asserted (logic 1)
0x1 uart_out2_n asserted (logic 0)
RW 0x0
2 out1

The value written to this location is inverted and driven out on uart_out1_n pin. Note that in Loopback mode (MCR[4] set to one), the uart_out1_n output is held inactive high while the value of this location is internally looped back to an input.

Value Description
0x0 uart_out1_n de-asserted (logic 1)
0x1 uart_out1_n asserted (logic 0)
RW 0x0
1 rts

This is used to directly control the Request to Send (uart_rts_n) output. The Request to Send (uart_rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the uart_rts_n signal is set low by programming MCR[1] (RTS) to a high. If Auto Flow Control is active (MCR[5] set to one) and FIFO's enable (FCR[0] set to one), the uart_rts_n output is controlled in the same way, but is also gated with the receiver FIFO threshold trigger (uart_rts_n is inactive high when above the threshold). The uart_rts_n signal will be de-asserted when MCR[1] is set low. Note that in Loopback mode (MCR[4] set to one), the uart_rts_n output is held inactive high while the value of this location is internally looped back to an input.

Value Description
0x0 uart_rts_n de-asserted (logic 1)
0x1 uart_rts_n asserted (logic 0)
RW 0x0
0 dtr

This is used to directly control the Data Terminal Ready output. The value written to this location is inverted and driven out on uart_dtr_n, that is: The Data Terminal Ready output is used to inform the modem or data set that the UART is ready to establish communications. Note that Loopback mode bit [4] of MCR is set to one, the uart_dtr_n output is held inactive high while the value of this location is internally looped back to an input.

Value Description
0x0 uart_dtr_n de-asserted (logic 1)
0x1 uart_dtr_n asserted (logic 0)
RW 0x0