ic_tx_abrt_source

This register has 16 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the ic_clr_tx_abrt register or the ic_clr_intr register is read. To clear Bit 9, the source of the abrt_sbyte_norstrt must be fixed first; RESTART must be enabled (ic_con[5]=1), the special bit must be cleared (ic_tar[11]), or the gc_or_start bit must be cleared (ic_tar[10]). Once the source of the abrt_sbyte_norstrt is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the abrt_sbyte_norstrt is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.

Module Instance	Base Address	Register Address
`i2c0`	`0xFFC04000`	`0xFFC04080`
`i2c1`	`0xFFC05000`	`0xFFC05080`
`i2c2`	`0xFFC06000`	`0xFFC06080`
`i2c3`	`0xFFC07000`	`0xFFC07080`

Offset: 0x80

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`tx_flush_cnt` RO 0x0									`Reserved`						`abrt_user_abrt` RO 0x0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`abrt_slvrd_intx` `RW 0x0`	`abrt_slv_arblost` `RW 0x0`	`abrt_slvflush_txfifo` `RW 0x0`	`arb_lost` `RW 0x0`	`abrt_master_dis` `RW 0x0`	`abrt_10b_rd_norstrt` `RW 0x0`	`abrt_sbyte_norstrt` `RW 0x0`	`abrt_hs_norstrt` `RW 0x0`	`abrt_sbyte_ackdet` `RW 0x0`	`abrt_hs_ackdet` `RW 0x0`	`abrt_gcall_read` `RW 0x0`	`abrt_gcall_noack` `RW 0x0`	`abrt_txdata_noack` `RW 0x0`	`abrt_10addr2_noack` `RW 0x0`	`abrt_10addr1_noack` `RW 0x0`	`abrt_7b_addr_noack` `RW 0x0`

ic_tx_abrt_source Fields

Bit	Name	Description	Access	Reset
31:23	`tx_flush_cnt`	This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of the I2C module: Master-Transmitter or Slave-Transmitter	RO	0x0
16	`abrt_user_abrt`	This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) Reset value: 0x0 Role of the I2C module: Master-Transmitter	RO	0x0
15	`abrt_slvrd_intx`	When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Role of I2C: Slave-Transmitter	`RW`	`0x0`
14	`abrt_slv_arblost`	Slave lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then I2C no longer own the bus. Role of I2C: Slave-Transmitter	`RW`	`0x0`
13	`abrt_slvflush_txfifo`	Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Role of I2C: Slave-Transmitter	`RW`	`0x0`
12	`arb_lost`	Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Note: I2C can be both master and slave at the same time. Role of i2c: Master-Transmitter or Slave-Transmitter	`RW`	`0x0`
11	`abrt_master_dis`	User tries to initiate a Master operation with the Master mode disabled. Role of I2C: Master-Transmitter or Master-Receiver	`RW`	`0x0`
10	`abrt_10b_rd_norstrt`	The restart is disabled (ic_restart_en bit (ic_con[5]) =0) and the master sends a read command in 10-bit addressing mode. Role of I2C: Master-Receiver	`RW`	`0x0`
9	`abrt_sbyte_norstrt`	To clear Bit 9, the source of then abrt_sbyte_norstrt must be fixed first; restart must be enabled (ic_con[5]=1), the SPECIAL bit must be cleared (ic_tar[11]), or the GC_OR_START bit must be cleared (ic_tar[10]). Once the source of the abrt_sbyte_norstrt is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the abrt_sbyte_norstrt is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. 1: The restart is disabled (IC_RESTART_EN bit (ic_con[5]) =0) and the user is trying to send a START Byte. Role of I2C: Master	`RW`	`0x0`
8	`abrt_hs_norstrt`	The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. Role of i2c: Master-Transmitter or Master-Receiver	`RW`	`0x0`
7	`abrt_sbyte_ackdet`	Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Role of i2c: Master	`RW`	`0x0`
6	`abrt_hs_ackdet`	Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Role of i2c: Master	`RW`	`0x0`
5	`abrt_gcall_read`	i2c in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). Role of i2c: Master-Transmitter	`RW`	`0x0`
4	`abrt_gcall_noack`	i2c in master mode sent a General Call and no slave on the bus acknowledged the General Call. Role of i2c: Master-Transmitter	`RW`	`0x0`
3	`abrt_txdata_noack`	This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Role of i2c: Master-Transmitter	`RW`	`0x0`
2	`abrt_10addr2_noack`	Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave. Role of i2c: Master-Transmitter or Master-Receiver	`RW`	`0x0`
1	`abrt_10addr1_noack`	Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Role of i2c: Master-Transmitter or Master-Receiver	`RW`	`0x0`
0	`abrt_7b_addr_noack`	Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Role of i2c: Master-Transmitter or Master-Receiver	`RW`	`0x0`