ic_clr_intr

Controls Interrupts
Module Instance Base Address Register Address
i2c0 0xFFC04000 0xFFC04040
i2c1 0xFFC05000 0xFFC05040
i2c2 0xFFC06000 0xFFC06040
i2c3 0xFFC07000 0xFFC07040

Offset: 0x40

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

clr_intr

RO 0x0

ic_clr_intr Fields

Bit Name Description Access Reset
0 clr_intr

Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the ic_tx_abrt_source register for an exception to clearing ic_tx_abrt_source.

RO 0x0