ic_intr_mask

These bits mask their corresponding interrupt status bits.
Module Instance Base Address Register Address
i2c0 0xFFC04000 0xFFC04030
i2c1 0xFFC05000 0xFFC05030
i2c2 0xFFC06000 0xFFC06030
i2c3 0xFFC07000 0xFFC07030

Offset: 0x30

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

m_gen_call

RW 0x1

m_start_det

RW 0x0

m_stop_det

RW 0x0

m_activity

RW 0x0

m_rx_done

RW 0x1

m_tx_abrt

RW 0x1

m_rd_req

RW 0x1

m_tx_empty

RW 0x1

m_tx_over

RW 0x1

m_rx_full

RW 0x1

m_rx_over

RW 0x1

m_rx_under

RW 0x1

ic_intr_mask Fields

Bit Name Description Access Reset
11 m_gen_call

Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling I2C or when the CPU reads bit 0 of the ic_clr_gen_call register. I2C stores the received data in the Rx buffer.

RW 0x1
10 m_start_det

Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether I2C is operating in slave or master mode.

RW 0x0
9 m_stop_det

Indicates whether a STOP condition has occurred on the I2C interface regardless of whether i2c is operating in slave or master mode.

RW 0x0
8 m_activity

This bit captures i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the i2c - Reading the ic_clr_activity register - Reading the ic_clr_intr register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the I2C module is idle, this bit remains set until cleared, indicating that there was activity on the bus.

RW 0x0
7 m_rx_done

When the I2C is acting as a slave-transmitter, this bit is set to 1, if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.

RW 0x1
6 m_tx_abrt

This bit indicates if I2C, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the ic_tx_abrt_source register indicates the reason why the transmit abort takes places. NOTE: The I2C flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register ic_clr_tx_abrt is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface.

RW 0x1
5 m_rd_req

This bit is set to 1 when I2C is acting as a slave and another I2C master is attempting to read data from I2C. The I2C holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the ic_data_cmd register. This bit is set to 0 just after the processor reads the ic_clr_rd_req register.

RW 0x1
4 m_tx_empty

This bit is set to 1 when the transmit buffer is at or below the threshold value set in the ic_tx_tl register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the ic_enable bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then this bit is set to 0.

RW 0x1
3 m_tx_over

Set during transmit if the transmit buffer is filled to 64 and the processor attempts to issue another I2C command by writing to the ic_data_cmd register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, then this interrupt is cleared.

RW 0x1
2 m_rx_full

Set when the receive buffer reaches or goes above the RX_TL threshold in the ic_rx_tl register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled ic_enable[0]=0, the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the ic_enable bit 0 is programmed with a 0, regardless of the activity that continues.

RW 0x1
1 m_rx_over

Set if the receive buffer is completely filled to 64 and an additional byte is received from an external I2C device. The I2C acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled ic_enable[0]=0, this bit keeps its level until the master or slave state machines go into idle, then this interrupt is cleared.

RW 0x1
0 m_rx_under

Set if the processor attempts to read the receive buffer when it is empty by reading from the ic_data_cmd register. If the module is disabled ic_enable[0]=0, this bit keeps its level until the master or slave state machines go into idle, and then this interrupt is cleared.

RW 0x1