ic_con

This register can be written only when the I2C is disabled, which corresponds to the Bit [0] of the Enable Register being set to 0. Writes at other times have no effect.

Module Instance	Base Address	Register Address
`i2c0`	`0xFFC04000`	`0xFFC04000`
`i2c1`	`0xFFC05000`	`0xFFC05000`
`i2c2`	`0xFFC06000`	`0xFFC06000`
`i2c3`	`0xFFC07000`	`0xFFC07000`

Offset: 0x0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`									`ic_slave_disable` `RW 0x1`	`ic_restart_en` `RW 0x1`	`ic_10bitaddr_master` `RW 0x1`	`ic_10bitaddr_slave` `RW 0x1`	`speed` `RW 0x2`		`master_mode` `RW 0x1`

ic_con Fields

Bit

Name

Description

Access

Reset

ic_slave_disable

This bit controls whether I2C has its slave disabled. The slave will be disabled, after reset. NOTE: Software should ensure that if this bit is written with 0, then bit [0] of this register should also be written with a 0.

Value	Description
0x1	slave disable
0x0	slave enable

RW

0x1

ic_restart_en

Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several I2C operations. When RESTART is disabled, the master is prohibited from performing the following functions - Changing direction within a transfer (split), - Sending a START BYTE, - High-speed mode operation, - Combined format transfers in 7-bit addressing modes, - Read operation with a 10-bit address, - Sending multiple bytes per transfer, By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple I2C transfers. If the above operations are performed, it will result in setting bit [6](tx_abort) of the Raw Interrupt Status Register.

Value	Description
0x0	restart master disable
0x1	restart master enable

RW

0x1

ic_10bitaddr_master

This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing mode when acting as a master.

Value	Description
0x0	7-bit addressing
0x1	10-bit addressing

RW

0x1

ic_10bitaddr_slave

When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses. In 7-bit addressing, only the lower 7 bits of the Slave Address Register are compared. The I2C responds will only respond to 10-bit addressing transfers that match the full 10 bits of the Slave Address register.

Value	Description
0x0	7-bit addressing
0x1	10-bit addressing

RW

0x1

2:1

speed

These bits control at which speed the I2C operates, its setting is relevant only if one is operating the I2C in master mode. Hardware protects against illegal values being programmed by software. This field should be programmed only with standard or fast speed.

Value	Description
0x1	standard mode (100 kbit/s)
0x2	fast mode (400 kbit/s)

RW

0x2

master_mode

This bit controls whether the i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1', then bit 6 should also be written with a '1'.

Value	Description
0x0	master disabled
0x1	master enabled

RW

0x1