dmacr

This register is used to enable the DMA Controller interface operation.
Module Instance Base Address Register Address
spim0 0xFFF00000 0xFFF0004C
spim1 0xFFF01000 0xFFF0104C

Offset: 0x4C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

tdmae

RW 0x0

rdmae

RW 0x0

dmacr Fields

Bit Name Description Access Reset
1 tdmae

This bit enables/disables the transmit FIFO DMA channel.

Value Description
0x0 Transmit DMA disabled
0x1 Transmit DMA enabled
RW 0x0
0 rdmae

This bit enables/disables the receive FIFO DMA channel.

Value Description
0x0 Receive DMA disabled
0x1 Receive DMA enabled
RW 0x0