imr

This register masks or enables all interrupts generated by the SPI Master.
Module Instance Base Address Register Address
spim0 0xFFF00000 0xFFF0002C
spim1 0xFFF01000 0xFFF0102C

Offset: 0x2C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

rxfim

RW 0x1

rxoim

RW 0x1

rxuim

RW 0x1

txoim

RW 0x1

txeim

RW 0x1

imr Fields

Bit Name Description Access Reset
4 rxfim

Full Mask

Value Description
0x0 spi_rxf_intr interrupt is masked (disabled)
0x1 spi_rxf_intr interrupt is enabled
RW 0x1
3 rxoim

Overflow Mask.

Value Description
0x0 spi_rxo_intr interrupt is masked (disabled)
0x1 spi_rxo_intr interrupt is enabled
RW 0x1
2 rxuim

Underflow Mask

Value Description
0x0 spi_rxu_intr interrupt is masked (disabled)
0x1 spi_rxu_intr interrupt is enabled
RW 0x1
1 txoim

Overflow Mask

Value Description
0x0 spi_txo_intr interrupt is masked (disabled)
0x1 spi_txo_intr interrupt is enabled
RW 0x1
0 txeim

Empty mask.

Value Description
0x0 spi_txe_intr interrupt is masked (disabled)
0x1 spi_txe_intr interrupt is enabled
RW 0x1