Interrupt_Enable

The Interrupt Enable register enables the interrupts reported by Register 5 (Status Register). Setting a bit to 1'b1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.
Module Instance Base Address Register Address
emac0 0xFF700000 0xFF70101C
emac1 0xFF702000 0xFF70301C

Offset: 0x101C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

nie

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

aie

RW 0x0

ere

RW 0x0

fbe

RW 0x0

Reserved

ete

RW 0x0

rwe

RW 0x0

rse

RW 0x0

rue

RW 0x0

rie

RW 0x0

une

RW 0x0

ove

RW 0x0

tje

RW 0x0

tue

RW 0x0

tse

RW 0x0

tie

RW 0x0

Interrupt_Enable Fields

Bit Name Description Access Reset
16 nie

When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): * Register 5[0]: Transmit Interrupt * Register 5[2]: Transmit Buffer Unavailable * Register 5[6]: Receive Interrupt * Register 5[14]: Early Receive Interrupt

Value Description
0x0 Normal Interrupt Summary Disabled
0x1 Normal Interrupt Summary Enabled
RW 0x0
15 aie

When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): * Register 5[1]: Transmit Process Stopped * Register 5[3]: Transmit Jabber Timeout * Register 5[4]: Receive Overflow * Register 5[5]: Transmit Underflow * Register 5[7]: Receive Buffer Unavailable * Register 5[8]: Receive Process Stopped * Register 5[9]: Receive Watchdog Timeout * Register 5[10]: Early Transmit Interrupt * Register 5[13]: Fatal Bus Error

Value Description
0x0 Abnormal Interrupt Summary Interrupt Disabled
0x1 Abnormal Interrupt Summary Interrupt Enabled
RW 0x0
14 ere

When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled.

Value Description
0x0 Early Receive Interrupt Disabled
0x1 Early Receive Interrupt Enabled
RW 0x0
13 fbe

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled.

Value Description
0x0 Fatal Bus Error Interrupt Disabled
0x1 Fatal Bus Error Interrupt Enabled
RW 0x0
10 ete

When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled.

Value Description
0x0 Early Transmit Interrupt Disabled
0x1 Early Transmit Interrupt Enabled
RW 0x0
9 rwe

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled.

Value Description
0x0 Receive Watchdog Timeout Interrupt Disabled
0x1 Receive Watchdog Timeout Interrupt Enabled
RW 0x0
8 rse

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled.

Value Description
0x0 Receive Stopped Interrupt Disabled
0x1 Receive Stopped Interrupt Enabled
RW 0x0
7 rue

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled.

RW 0x0
6 rie

When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled.

Value Description
0x0 Receive Interrupt Disabled
0x1 Receive Interrupt Enabled
RW 0x0
5 une

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled.

Value Description
0x0 Underflow Interrupt Disabled
0x1 Underflow Interrupt Enabled
RW 0x0
4 ove

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled.

Value Description
0x0 Transmit Overflow Interrupt Disabled
0x1 Transmit Overflow Interrupt Enabled
RW 0x0
3 tje

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled.

Value Description
0x0 Transmit Jabber Timeout Interrupt Disabled
0x1 Transmit Jabber Timeout Interrupt Enabled
RW 0x0
2 tue

When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled.

Value Description
0x0 Transmit Buffer Unavailable Interrupt Disabled
0x1 Transmit Buffer Unavailable Interrupt Enabled
RW 0x0
1 tse

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled.

Value Description
0x0 Transmit Stopped Interrupt Disabled
0x1 Transmit Stopped Interrupt Enabled
RW 0x0
0 tie

When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled.

Value Description
0x0 Transmit Interrupt Disabled
0x1 Transmit Interrupt Enabled
RW 0x0