MMC_Control

The MMC Control register establishes the operating mode of the management counters. Note: The bit 0 (Counters Reset) has higher priority than bit 4 (Counter Preset). Therefore, when the Software tries to set both bits in the same write cycle, all counters are cleared and the bit 4 is not set.

Module Instance	Base Address	Register Address
`emac0`	`0xFF700000`	`0xFF700100`
`emac1`	`0xFF702000`	`0xFF702100`

Offset: 0x100

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`ucdbc` `RW 0x0`	`Reserved`		`cntprstlvl` `RW 0x0`	`cntprst` `RW 0x0`	`cntfreez` `RW 0x0`	`rstonrd` `RW 0x0`	`cntstopro` `RW 0x0`	`cntrst` `RW 0x0`

MMC_Control Fields

Bit

Name

Description

Access

Reset

ucdbc

When set, this bit enables MAC to update all the related MMC Counters for Broadcast frames dropped due to setting of DBF bit (Disable Broadcast Frames) of MAC Filter Register at offset 0x0004. When reset, MMC Counters are not updated for dropped Broadcast frames.

RW

0x0

cntprstlvl

When low and bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half - 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half - 16). When this bit is high and bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full - 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full - 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0.

Value	Description
0x0	Preset All Counters to almost-half
0x1	Present All Counters almost-full

RW

0x0

cntprst

When this bit is set, all counters are initialized or preset to almost full or almost half according to bit 5. This bit is cleared automatically after 1 clock cycle. This bit, along with bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full.

Value	Description
0x0	Counters not preset
0x1	Counters preset to full or almost full

RW

0x0

cntfreez

When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode.

Value	Description
0x0	Update MMC Counters
0x1	Freeze MMC counters to current value

RW

0x0

rstonrd

When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (bits[7:0]) is read.

Value	Description
0x0	No reset after read
0x1	Reset after read

RW

0x0

cntstopro

When this bit is set, after reaching maximum value, the counter does not roll over to zero.

Value	Description
0x0	Counter Roll Over
0x1	Counter does not Roll Over

RW

0x0

cntrst

When this bit is set, all counters are reset. This bit is cleared automatically after one clock cycle.

Value	Description
0x0	Auto cleared after 1 clock cycle
0x1	All Counters Reset

RW

0x0