LPI_Control_Status

The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read.
Module Instance Base Address Register Address
emac0 0xFF700000 0xFF700030
emac1 0xFF702000 0xFF702030

Offset: 0x30

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

lpitxa

RW 0x0

plsen

RW 0x0

pls

RW 0x0

lpien

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

rlpist

RO 0x0

tlpist

RO 0x0

Reserved

rlpiex

RO 0x0

rlpien

RO 0x0

tlpiex

RO 0x0

tlpien

RO 0x0

LPI_Control_Status Fields

Bit Name Description Access Reset
19 lpitxa

This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set, in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode.

Value Description
0x0 LPI TX Automate Disabled
0x1 LPI TX Automate Enabled
RW 0x0
18 plsen

This bit enables the link status received on the RGMII receive paths to be used for activating the LPI LS TIMER. When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit.

Value Description
0x0 MAC Ignores Link Status Bits
0x1 MAC Uses Link Status Bits
RW 0x0
17 pls

This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. When set, the link is considered to be okay (up) and when reset, the link is considered to be down.

Value Description
0x0 Link Down
0x1 Link Up (okay)
RW 0x0
16 lpien

When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission.

Value Description
0x0 MAC Transmitter exit LPI State
0x1 MAC Transmitter enters LPI State
RW 0x0
9 rlpist

When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface.

Value Description
0x0 MAC is not receiving LPI Pattern
0x1 MAC receiving LPI Pattern
RO 0x0
8 tlpist

When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface.

Value Description
0x0 MAC Transmitting LPI Pattern
0x1 MAC Transmitting LPI Pattern
RO 0x0
3 rlpiex

When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of l3_sp_clk.

Value Description
0x0 MAC RX receiving LPI Patterns
0x1 MAC RX Stopped receiving LPI Patterns
RO 0x0
2 rlpien

When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of l3_sp_clk.

Value Description
0x0 MAC Receiver Not In LPI State
0x1 MAC Receiver In LPI State
RO 0x0
1 tlpiex

When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register.

Value Description
0x0 MAC Transmitter Non LPI State
0x1 MAC Transmitter Exited LPI State
RO 0x0
0 tlpien

When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register.

Value Description
0x0 MAC Transmitter Not in LPI State
0x1 MAC Transmitter Entered LPI State
RO 0x0