indwr

Module Instance Base Address Register Address
qspiregs 0xFF705000 0xFF705070

Offset: 0x70

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

indcnt

RO 0x0

inddone

RW 0x0

rdqueued

RO 0x0

sramfull

RO 0x0

rdstat

RO 0x0

cancel

RW 0x0

start

RW 0x0

indwr Fields

Bit Name Description Access Reset
7:6 indcnt

This field contains the count of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5).

 RO 0x0
5 inddone

This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it.

Value Description
0x1 Indirect operation completed
0x0 No Action
RW 0x0
4 rdqueued

Two indirect write operations have been queued

Value Description
0x1 Two Indirect write operation
0x0 No Action
RO 0x0
3 sramfull

RO 0x0
2 rdstat

Indirect write operation in progress (status)

Value Description
0x1 Indirect write operation
0x0 No Action
RO 0x0
1 cancel

Writing a 1 to this bit will cancel all ongoing indirect write operations.

Value Description
0x1 Cancel Indirect write operation
0x0 No Action
RW 0x0
0 start

Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation.

Value Description
0x1 Trigger indirect write operation
0x0 No Action
RW 0x0