rintsts

Interrupt Status Before Masking.
Module Instance Base Address Register Address
sdmmc 0xFF704000 0xFF704044

Offset: 0x44

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

sdio_interrupt

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ebe

RW 0x0

acd

RW 0x0

sbe

RW 0x0

hle

RW 0x0

frun

RW 0x0

hto

RW 0x0

bds

RW 0x0

bar

RW 0x0

dcrc

RW 0x0

rcrc

RW 0x0

rxdr

RW 0x0

txdr

RW 0x0

dto

RW 0x0

cmd

RW 0x0

re

RW 0x0

cd

RW 0x0

rintsts Fields

Bit Name Description Access Reset
16 sdio_interrupt

Interrupt from SDIO card.

Value Description
0x1 SDIO interrupt from card bit
0x0 No SDIO interrupt from card bi
RW 0x0
15 ebe

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 End-bit error (read)/write no CRC (EBE)
0x1 Clears End-bit error (read)/write no CRC (EBE)
RW 0x0
14 acd

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Auto command done (ACD)
0x1 Clear Auto command done (ACD
RW 0x0
13 sbe

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Start-bit error (SBE)
0x1 Clears Start-bit error (SBE)
RW 0x0
12 hle

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Hardware locked write error (HLE)
0x1 Clears Hardware locked write error (HLE)
RW 0x0
11 frun

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 FIFO underrun/overrun error (FRUN)
0x1 Clear FIFO underrun/overrun error (FRUN)
RW 0x0
10 hto

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Data starvation-by-host timeout (HTO) /Volt_switch_int
0x1 Clears Data starvation-by-host timeout (HTO) /Volt_switch_int
RW 0x0
9 bds

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Data read timeout (DRTO)/Boot Data Start (BDS)
0x1 Clears Data read timeout (DRTO)/Boot Data Start (BDS)
RW 0x0
8 bar

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Response timeout (RTO)/Boot Ack Received (BAR)
0x1 Clears Response timeout (RTO)/Boot Ack Received (BAR)
RW 0x0
7 dcrc

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Data CRC error (DCRC)
0x1 Clears Data CRC error (DCRC)
RW 0x0
6 rcrc

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Response CRC error (RCRC)
0x1 Clears Response CRC error (RCRC)
RW 0x0
5 rxdr

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Receive FIFO data request (RXDR)
0x1 Clears Receive FIFO data request (RXDR)
RW 0x0
4 txdr

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Transmit FIFO data request (TXDR)
0x1 Clears Transmit FIFO data request (TXDR)
RW 0x0
3 dto

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Data transfer over (DTO)
0x1 Clears Data transfer over (DTO)
RW 0x0
2 cmd

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Command done (CD)
0x1 Clears Command done (CD)
RW 0x0
1 re

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Response error (RE)
0x1 Clears Response error (RE)
RW 0x0
0 cd

Writes to bits clear status bit. Value of 1 clears status bit, and value of 0 leaves bit intact. Bits are logged regardless of interrupt mask status.

Value Description
0x0 Card detect (CD)
0x1 Clears Card detect (CD)
RW 0x0