cmd

This register issues various commands.
Module Instance Base Address Register Address
sdmmc 0xFF704000 0xFF70402C

Offset: 0x2C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

start_cmd

RW 0x0

Reserved

use_hold_reg

RW 0x1

volt_switch

RW 0x0

boot_mode

RW 0x0

disable_boot

RW 0x0

expect_boot_ack

RW 0x0

enable_boot

RW 0x0

ccs_expected

RW 0x0

read_ceata_device

RW 0x0

update_clock_registers_only

RW 0x0

card_number

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

send_initialization

RW 0x0

stop_abort_cmd

RW 0x0

wait_prvdata_complete

RW 0x0

send_auto_stop

RW 0x0

transfer_mode

RW 0x0

read_write

RW 0x0

data_expected

RW 0x0

check_response_crc

RW 0x0

response_length

RW 0x0

response_expect

RW 0x0

cmd_index

RW 0x0

cmd Fields

Bit Name Description Access Reset
31 start_cmd

Once command is taken by CIU, bit is cleared. If Start Cmd issued host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in raw interrupt register.

Value Description
0x0 No Start Cmd
0x1 Start Cmd Issued
RW 0x0
29 use_hold_reg

Set to one for SDR12 and SDR25 (with non-zero phase-shifted cclk_in_drv); zero phase shift is not allowed in these modes. -Set to 1'b0 for SDR50, SDR104, and DDR50 (with zero phase-shifted cclk_in_drv). -Set to 1'b1 for SDR50, SDR104, and DDR50 (with non-zero phase-shifted cclk_in_drv).

Value Description
0x0 CMD and DATA sent to card bypassing HOLD Register
0x1 CMD and DATA sent to card through the HOLD Register
RW 0x1
28 volt_switch

Voltage switch bit. When set must be set for CMD11 only.

Value Description
0x0 No voltage switching - default
0x1 Voltage switching enabled
RW 0x0
27 boot_mode

Type of Boot Mode.

Value Description
0x0 Mandatory Boot Operation
0x1 Alternate Boot Operation
RW 0x0
26 disable_boot

When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together.

Value Description
0x0 Boot not Terminated
0x1 Terminate Boot
RW 0x0
25 expect_boot_ack

When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card.

Value Description
0x0 No Boot ACK
0x1 Expect Boot ACK
RW 0x0
24 enable_boot

This bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together

Value Description
0x0 Disable Boot
0x1 Enable Boot
RW 0x0
23 ccs_expected

If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked.

Value Description
0x0 Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device
0x1 Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device
RW 0x0
22 read_ceata_device

Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device.

Value Description
0x0 Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device
0x1 Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device
RW 0x0
21 update_clock_registers_only

Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards.

Value Description
0x0 Normal command sequence
0x1 Do not send commands, just update clock register value into card clock domain
RW 0x0
20:16 card_number

Card number in use must always be 0.

 RW 0x0
15 send_initialization

After power on, 80 clocks must be sent to the card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory).

Value Description
0x0 Do not send initialization sequence (80 clocks of 1) before sending this command
0x1 Send initialization sequence before sending this command
RW 0x0
14 stop_abort_cmd

When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot. Note: If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0.

Value Description
0x0 Don't stop or abort command to stop current data transfer in progress
0x1 Stop or Abort command, intended to stop current data transfer in progress
RW 0x0
13 wait_prvdata_complete

Determines when command is sent. The send command at once option is typically used to query status of card during data transfer or to stop current data transfer.

Value Description
0x0 Send command at once
0x1 Wait for previous data transfer completion
RW 0x0
12 send_auto_stop

When set, SD/MMC sends stop command to SD_MMC_CEATA cards at end of data transfer. Determine the following: *-when send_auto_stop bit should be set, since some data transfers do not need explicit stop commands. *-open-ended transfers that software should explicitly send to stop command. Additionally, when resume is sent to resume- suspended memory access of SD-Combo card, bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card.

Value Description
0x0 No stop command sent at end of data transfer
0x1 Send stop command at end of data transfer
RW 0x0
11 transfer_mode

Block transfer command. Don't care if no data expected

Value Description
0x0 Block data transfer command
0x1 Stream data transfer command
RW 0x0
10 read_write

Read/Write from card. Don't care if no data transfer expected.

Value Description
0x0 Read from card
0x1 Write to card
RW 0x0
9 data_expected

Set decision on data transfer expecetd or not.

Value Description
0x0 No data transfer expected (read/write)
0x1 Data transfer expected (read/write)
RW 0x0
8 check_response_crc

Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller.

Value Description
0x0 Do not check response CRC
0x1 Check Response CRC
RW 0x0
7 response_length

Provides long and short response

Value Description
0x0 Short response expected from card
0x1 Long response expected from card
RW 0x0
6 response_expect

Response expected from card.

Value Description
0x0 No response expected from card
0x1 Response expected from card
RW 0x0
5:0 cmd_index

Tracks the command index number. Values from 0-31.

 RW 0x0