rdwr_en_hi_cnt
Read/Write Enable high pulse width
| Module Instance | Base Address | Register Address |
|---|---|---|
| nandregs | 0xFFB80000 | 0xFFB80200 |
Offset: 0x200
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
value RW 0xC |
||||||||||||||
rdwr_en_hi_cnt Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 4:0 | value | Number of nand_mp_clk cycles that read or write enable will kept high to meet the min Treh/Tweh parameter of the device. The value in this register plus rdwr_en_lo_cnt register value should meet the min cycle time of the device connected. The default value is calculated assuming the max nand_mp_clk time period of 4ns to work with ONFI Mode 0 mode of 100ns device cycle time. This assumes a 1x/4x clocking scheme. |
RW | 0xC |