prefetch_mode
Enables read data prefetching to faster performance
| Module Instance | Base Address | Register Address |
|---|---|---|
| nandregs | 0xFFB80000 | 0xFFB800C0 |
Offset: 0xC0
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
prefetch_burst_length RW 0x0 |
Reserved |
prefetch_en RW 0x1 |
|||||||||||||
prefetch_mode Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 15:4 | prefetch_burst_length | If prefetch_en is set and prefetch_burst_length is set to ZERO, the controller will start prefetching data only after the receiving the first Map01 read command for the page. If prefetch_en is set and prefetch_burst_length is set to a non-ZERO, valid value, the controller will start prefetching data corresponding to this value even before the first Map01 for the current page has been received. The value written here should be in bytes. |
RW | 0x0 |
| 0 | prefetch_en | Enable prefetch of Data |
RW | 0x1 |