l4osc1
Controls security settings for L4 OSC1 peripherals.
| Module Instance | Base Address | Register Address |
|---|---|---|
| l3regs | 0xFF800000 | 0xFF800014 |
Offset: 0x14
Access: WO
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
osc1timer1 WO 0x0 |
osc1timer0 WO 0x0 |
sysmgr WO 0x0 |
rstmgr WO 0x0 |
clkmgr WO 0x0 |
l4wd1 WO 0x0 |
l4wd0 WO 0x0 |
||||||||
l4osc1 Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 6 | osc1timer1 | Controls whether secure or non-secure masters can access the OSC1 Timer 1 slave.
|
WO | 0x0 | ||||||
| 5 | osc1timer0 | Controls whether secure or non-secure masters can access the OSC1 Timer 0 slave.
|
WO | 0x0 | ||||||
| 4 | sysmgr | Controls whether secure or non-secure masters can access the System Manager slave.
|
WO | 0x0 | ||||||
| 3 | rstmgr | Controls whether secure or non-secure masters can access the Reset Manager slave.
|
WO | 0x0 | ||||||
| 2 | clkmgr | Controls whether secure or non-secure masters can access the Clock Manager slave.
|
WO | 0x0 | ||||||
| 1 | l4wd1 | Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0 slave.
|
WO | 0x0 | ||||||
| 0 | l4wd0 | Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0 slave.
|
WO | 0x0 |