32-bit Master Register Descriptions Registers associated with the 32-bit AXI master interface. This master provides access to slaves in the FPGA. Offset: 0x3000 fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. wr_tidemark Controls the release of the transaction in the write data FIFO. fn_mod Sets the block issuing capability to multiple or single outstanding transactions. Related reference FPGA2HPS AXI Bridge Registers Register Descriptions HPS2FPGA AXI Bridge Registers Register Descriptions