32-bit Master Register Descriptions Registers associated with the 32-bit AXI master interface. These registers are only active when the HPS2FPGA AXI Bridge is configured with a 32-bit FPGA AXI master interface. Offset: 0x0 fn_mod2 Controls bypass merge of upsizing/downsizing. fn_mod Sets the block issuing capability to multiple or single outstanding transactions. Related reference 128-bit Master Register Descriptions