NAND Flash Controller Register Group Register Descriptions Registers related to NAND Flash Controller which aren't located in the NAND Flash Controller itself. Offset: 0x110 bootstrap Bootstrap fields sampled by NAND Flash Controller when released from reset. All fields are reset by a cold or warm reset. l3master Controls the L3 master ARCACHE and AWCACHE AXI signals. These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation All fields are reset by a cold or warm reset.