GENERALIO10

This register is used to control the peripherals connected to spim0_mosi Only reset by a cold reset (ignores warm reset). NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections.
Module Instance Base Address Register Address
sysmgr 0xFFD08000 0xFFD084A8

Offset: 0x4A8

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

sel

RW 0x0

GENERALIO10 Fields

Bit Name Description Access Reset
1:0 sel

Select peripheral signals connected spim0_mosi. 0 : Pin is connected to GPIO/LoanIO number 58. 1 : Pin is connected to Peripheral signal UART0.RTS. 2 : Pin is connected to Peripheral signal I2C1.SCL. 3 : Pin is connected to Peripheral signal SPIM0.MOSI.

RW 0x0