sdmmc

This register is used to enable ECC on the SDMMC RAM.ECC errors can be injected into the write path using bits in this register. Only reset by a cold reset (ignores warm reset).

Module Instance	Base Address	Register Address
`sysmgr`	`0xFFD08000`	`0xFFD0816C`

Offset: 0x16C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`derrportb` `RW 0x0`	`serrportb` `RW 0x0`	`derrporta` `RW 0x0`	`serrporta` `RW 0x0`	`injdportb` `RW 0x0`	`injsportb` `RW 0x0`	`injdporta` `RW 0x0`	`injsporta` `RW 0x0`	`en` `RW 0x0`

sdmmc Fields

Bit	Name	Description	Access	Reset
8	`derrportb`	This bit is an interrupt status bit for SDMMC Port B RAM ECC double bit, non-correctable error. It is set by hardware when double bit, non-correctable error occurs in SDMMC Port B RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
7	`serrportb`	This bit is an interrupt status bit for SDMMC Port B RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in SDMMC Port B RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
6	`derrporta`	This bit is an interrupt status bit for SDMMC Port A RAM ECC double bit, non-correctable error. It is set by hardware when double bit, non-correctable error occurs in SDMMC Port A RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
5	`serrporta`	This bit is an interrupt status bit for SDMMC Port A RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in SDMMC Port A RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
4	`injdportb`	Changing this bit from zero to one injects a double, non-correctable error into the SDMMC RAM at Port B. This only injects one double bit error into the SDMMC RAM at Port B.	`RW`	`0x0`
3	`injsportb`	Changing this bit from zero to one injects a single, correctable error into the SDMMC RAM at Port B. This only injects one error into the SDMMC RAM at Port B.	`RW`	`0x0`
2	`injdporta`	Changing this bit from zero to one injects a double, non-correctable error into the SDMMC RAM at Port A. This only injects one double bit error into the SDMMC RAM at Port A.	`RW`	`0x0`
1	`injsporta`	Changing this bit from zero to one injects a single, correctable error into the SDMMC RAM at Port A. This only injects one error into the SDMMC RAM at Port A.	`RW`	`0x0`
0	`en`	Enable ECC for SDMMC RAM	`RW`	`0x0`