nand

This register is used to enable ECC on the NAND RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error. Only reset by a cold reset (ignores warm reset).

Module Instance	Base Address	Register Address
`sysmgr`	`0xFFD08000`	`0xFFD08164`

Offset: 0x164

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`			`rdfifoderr` `RW 0x0`	`rdfifoserr` `RW 0x0`	`wrfifoderr` `RW 0x0`	`wrfifoserr` `RW 0x0`	`eccbufderr` `RW 0x0`	`eccbufserr` `RW 0x0`	`rdfifoinjd` `RW 0x0`	`rdfifoinjs` `RW 0x0`	`wrfifoinjd` `RW 0x0`	`wrfifoinjs` `RW 0x0`	`eccbufinjd` `RW 0x0`	`eccbufinjs` `RW 0x0`	`en` `RW 0x0`

nand Fields

Bit	Name	Description	Access	Reset
12	`rdfifoderr`	This bit is an interrupt status bit for NAND RDFIFO RAM ECC double bit, non-correctable error. It is set by hardware when double bit, non-correctable error occurs in NAND RDFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
11	`rdfifoserr`	This bit is an interrupt status bit for NAND RDFIFO RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in NAND RDFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
10	`wrfifoderr`	This bit is an interrupt status bit for NAND WRFIFO RAM ECC double bit, non-correctable error. It is set by hardware when double bit, non-correctable error occurs in NAND WRFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
9	`wrfifoserr`	This bit is an interrupt status bit for NAND WRFIFO RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in NAND WRFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
8	`eccbufderr`	This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC double bit, non-correctable error. It is set by hardware when double bit, non-correctable error occurs in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
7	`eccbufserr`	This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear the interrupt status.	`RW`	`0x0`
6	`rdfifoinjd`	Changing this bit from zero to one injects a double, non-correctable error into the NAND RDFIFO RAM. This only injects one double bit error into the NAND RDFIFO RAM.	`RW`	`0x0`
5	`rdfifoinjs`	Changing this bit from zero to one injects a single, correctable error into the NAND RDFIFO RAM. This only injects one error into the NAND RDFIFO RAM.	`RW`	`0x0`
4	`wrfifoinjd`	Changing this bit from zero to one injects a double, non-correctable error into the NAND WRFIFO RAM. This only injects one double bit error into the NAND WRFIFO RAM.	`RW`	`0x0`
3	`wrfifoinjs`	Changing this bit from zero to one injects a single, correctable error into the NAND WRFIFO RAM. This only injects one error into the NAND WRFIFO RAM.	`RW`	`0x0`
2	`eccbufinjd`	Changing this bit from zero to one injects a double, non-correctable error into the NAND ECCBUFFER RAM. This only injects one double bit error into the NAND ECCBUFFER RAM.	`RW`	`0x0`
1	`eccbufinjs`	Changing this bit from zero to one injects a single, correctable error into the NAND ECCBUFFER RAM. This only injects one error into the NAND ECCBUFFER RAM.	`RW`	`0x0`
0	`en`	Enable ECC for NAND RAM	`RW`	`0x0`