ctrl

Registers used by the EMACs. All fields are reset by a cold or warm reset.
Module Instance Base Address Register Address
sysmgr 0xFFD08000 0xFFD08060

Offset: 0x60

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

ptpclksel_1

RW 0x0

ptpclksel_0

RW 0x0

physel_1

RW 0x2

physel_0

RW 0x2

ctrl Fields

Bit Name Description Access Reset
5 ptpclksel_1

Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC module when it exits from reset. The field array index corresponds to the EMAC index.

Value Description
0x0 Selects osc1_clk
0x1 Selects fpga_ptp_ref_clk
RW 0x0
4 ptpclksel_0

Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC module when it exits from reset. The field array index corresponds to the EMAC index.

Value Description
0x0 Selects osc1_clk
0x1 Selects fpga_ptp_ref_clk
RW 0x0
3:2 physel_1

Controls the PHY interface selection of the EMACs. This is sampled by an EMAC module when it exits from reset. The associated enum defines the allowed values. The field array index corresponds to the EMAC index.

Value Description
0x0 Select GMII/MII PHY interface
0x1 Select RGMII PHY interface
0x2 Select RMII PHY interface
RW 0x2
1:0 physel_0

Controls the PHY interface selection of the EMACs. This is sampled by an EMAC module when it exits from reset. The associated enum defines the allowed values. The field array index corresponds to the EMAC index.

Value Description
0x0 Select GMII/MII PHY interface
0x1 Select RGMII PHY interface
0x2 Select RMII PHY interface
RW 0x2