gpio_inten
Allows each bit of Port A to be configured to generate an interrupt or not.
| Module Instance | Base Address | Register Address |
|---|---|---|
| fpgamgrregs | 0xFF706000 | 0xFF706830 |
Offset: 0x830
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
fpo RW 0x0 |
cdp RW 0x0 |
nsp RW 0x0 |
ncp RW 0x0 |
prd RW 0x0 |
pre RW 0x0 |
prr RW 0x0 |
ccd RW 0x0 |
crc RW 0x0 |
id RW 0x0 |
cd RW 0x0 |
ns RW 0x0 |
|||
gpio_inten Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 11 | fpo | Enables interrupt generation for FPGA_POWER_ON
|
RW | 0x0 | ||||||
| 10 | cdp | Enables interrupt generation for CONF_DONE Pin
|
RW | 0x0 | ||||||
| 9 | nsp | Enables interrupt generation for nSTATUS Pin
|
RW | 0x0 | ||||||
| 8 | ncp | Enables interrupt generation for nCONFIG Pin
|
RW | 0x0 | ||||||
| 7 | prd | Enables interrupt generation for PR_DONE
|
RW | 0x0 | ||||||
| 6 | pre | Enables interrupt generation for PR_ERROR
|
RW | 0x0 | ||||||
| 5 | prr | Enables interrupt generation for PR_READY
|
RW | 0x0 | ||||||
| 4 | ccd | Enables interrupt generation for CVP_CONF_DONE
|
RW | 0x0 | ||||||
| 3 | crc | Enables interrupt generation for CRC_ERROR
|
RW | 0x0 | ||||||
| 2 | id | Enables interrupt generation for INIT_DONE
|
RW | 0x0 | ||||||
| 1 | cd | Enables interrupt generation for CONF_DONE
|
RW | 0x0 | ||||||
| 0 | ns | Enables interrupt generation for nSTATUS
|
RW | 0x0 |