en

Contains fields that control the SDRAM Clock Group enables generated from the SDRAM PLL clock outputs. 1: The clock is enabled. 0: The clock is disabled. Fields are only reset by a cold reset.

Module Instance	Base Address	Register Address
`clkmgr`	`0xFFD04000`	`0xFFD040D8`

Offset: 0xD8

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`												`s2fuser2clk` `RW 0x1`	`ddrdqclk` `RW 0x1`	`ddr2xdqsclk` `RW 0x1`	`ddrdqsclk` `RW 0x1`

en Fields

Bit	Name	Description	Access	Reset
3	`s2fuser2clk`	Enables clock s2f_user2_clk output. and user documentation refer to s2f_user2_clk as h2f_user2_clk.	`RW`	`0x1`
2	`ddrdqclk`	Enables clock ddr_dq_clk output	`RW`	`0x1`
1	`ddr2xdqsclk`	Enables clock ddr_2x_dqs_clk output	`RW`	`0x1`
0	`ddrdqsclk`	Enables clock ddr_dqs_clk output	`RW`	`0x1`