tracediv

Contains a field that controls the clock divider for the debug trace clock derived from the Main PLL Only reset by a cold reset.
Module Instance Base Address Register Address
clkmgr 0xFFD04000 0xFFD0406C

Offset: 0x6C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

traceclk

RW 0x0

tracediv Fields

Bit Name Description Access Reset
2:0 traceclk

The dbg_trace_clk is divided down from the C2 output of the Main PLL by the value specified in this field.

Value Description
0x0 Divide By 1
0x1 Divide By 2
0x2 Divide By 4
0x3 Divide By 8
0x4 Divide By 16
0x5 Reserved
0x6 Reserved
0x7 Reserved
RW 0x0