maindiv
Contains fields that control clock dividers for main clocks derived from the Main PLL
Fields are only reset by a cold reset.
| Module Instance | Base Address | Register Address |
|---|---|---|
| clkmgr | 0xFFD04000 | 0xFFD04064 |
Offset: 0x64
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
l4spclk RW 0x0 |
l4mpclk RW 0x0 |
l3spclk RW 0x0 |
l3mpclk RW 0x0 |
|||||||||||
maindiv Fields
| Bit | Name | Description | Access | Reset | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9:7 | l4spclk | The l4_sp_clk is divided down from the periph_base_clk by the value specified in this field.
|
RW | 0x0 | ||||||||||||||||||
| 6:4 | l4mpclk | The l4_mp_clk is divided down from the periph_base_clk by the value specified in this field.
|
RW | 0x0 | ||||||||||||||||||
| 3:2 | l3spclk | The l3_sp_clk is divided down from the l3_mp_clk by the value specified in this field.
|
RW | 0x0 | ||||||||||||||||||
| 1:0 | l3mpclk | The l3_mp_clk is divided down from the l3_main_clk by the value specified in this field.
|
RW | 0x0 |