bypass

Contains fields that control bypassing each PLL.
Module Instance Base Address Register Address
clkmgr 0xFFD04000 0xFFD04004

Offset: 0x4

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

perpllsrc

RW 0x0

perpll

RW 0x1

sdrpllsrc

RW 0x0

sdrpll

RW 0x1

mainpll

RW 0x1

bypass Fields

Bit Name Description Access Reset
4 perpllsrc

This bit defines the bypass source for Peripheral PLL. When changing fields that affect VCO lock the PLL must be bypassed and this bit must be set to OSC1_CLK. The reset value for this bit is applied on a cold reset. Warm reset has no effect on this bit.

Value Description
0x0 Select EOSC1
0x1 Select PLL Input Mux
RW 0x0
3 perpll

When set, causes the Peripheral PLL VCO and counters to be bypassed so that all clocks generated by the Peripheral PLL are directly driven from either eosc1_clk or the Peripheral PLL input clock. The bypass clock source for Peripheral PLL is determined by the Peripheral PLL Bypass Source Register bit. The reset value for this bit is applied on a cold reset. Warm reset has no effect on this bit.

RW 0x1
2 sdrpllsrc

This bit defines the bypass source forSDRAM PLL. When changing fields that affect VCO lock the PLL must be bypassed and this bit must be set to OSC1_CLK. The reset value for this bit is applied on a cold reset. Warm reset has no effect on this bit.

Value Description
0x0 Select EOSC1
0x1 Select PLL Input Mux
RW 0x0
1 sdrpll

When set, causes the SDRAM PLL VCO and counters to be bypassed so that all clocks generated by the SDRAM PLL are directly driven from either eosc1_clk or the SDRAM PLL input clock. The bypass clock source for SDRAM PLL is determined by the SDRAM PLL Bypass Source Register bit. The reset value for this bit is applied on a cold reset. Warm reset has no effect on this bit.

RW 0x1
0 mainpll

When set, causes the Main PLL VCO and counters to be bypassed so that all clocks generated by the Main PLL are directly driven from the Main PLL input clock. The bypass source for Main PLL is the external eosc1_clk. The reset value for this bit is applied on a cold reset. Warm reset has no effect on this bit.

RW 0x1