ctrl

Contains fields that control the entire Clock Manager.

Module Instance	Base Address	Register Address
`clkmgr`	`0xFFD04000`	`0xFFD04000`

Offset: 0x0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`													`ensfmdwr` `RW 0x1`	`Reserved`	`safemode` `RW 0x1`

ctrl Fields

Bit	Name	Description	Access	Reset
2	`ensfmdwr`	When set the Clock Manager will respond to a Safe Mode request from the Reset Manager on a warm reset by setting the Safe Mode bit. When clear the clock manager will not set the Safe Mode bit on a warm reset This bit is cleared on a cold reset. Warm reset has no effect on this bit. By default, this bit is set by the preloader during the initial boot up stage. Intel recommends that you do not clear this bit during any of the later HPS boot stages.	`RW`	`0x1`
0	`safemode`	When set the Clock Manager is in Safe Mode. In Safe Mode Clock Manager register settings defining clock behavior are ignored and clocks are set to a Safe Mode state.In Safe Mode all clocks with the optional exception of debug clocks, are directly generated from the EOSC1 clock input, all PLLs are bypassed, all programmable dividers are set to 1 and all clocks are enabled. This bit should only be cleared when clocks have been correctly configured This field is set on a cold reset and optionally on a warm reset and may not be set by SW.	`RW`	`0x1`

Bit

Name

Description

Access

Reset

ensfmdwr

When set the Clock Manager will respond to a Safe Mode request from the Reset Manager on a warm reset by setting the Safe Mode bit. When clear the clock manager will not set the Safe Mode bit on a warm reset This bit is cleared on a cold reset. Warm reset has no effect on this bit.

By default, this bit is set by the preloader during the initial boot up stage. Intel recommends that you do not clear this bit during any of the later HPS boot stages.

RW

0x1

safemode

When set the Clock Manager is in Safe Mode. In Safe Mode Clock Manager register settings defining clock behavior are ignored and clocks are set to a Safe Mode state.In Safe Mode all clocks with the optional exception of debug clocks, are directly generated from the EOSC1 clock input, all PLLs are bypassed, all programmable dividers are set to 1 and all clocks are enabled. This bit should only be cleared when clocks have been correctly configured This field is set on a cold reset and optionally on a warm reset and may not be set by SW.

RW

0x1