isr

         Interrupt Status Register
      
Module Instance Base Address Register Address
i_spim_0_spim 0xFFDA4000 0xFFDA4030
i_spim_1_spim 0xFFDA5000 0xFFDA5030

Offset: 0x30

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mstis

RO 0x0

rxfis

RO 0x0

rxois

RO 0x0

rxuis

RO 0x0

txois

RO 0x0

txeis

RO 0x0

isr Fields

Bit Name Description Access Reset
5 mstis
Multi-Master Contention Interrupt Status. This bit field is not present
if the DW_apb_ssi is configured as a serial-slave device.
0 = ssi_mst_intr interrupt not active after masking
1 = ssi_mst_intr interrupt is active after masking
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
4 rxfis
Receive FIFO Full Interrupt Status
0 = ssi_rxf_intr interrupt is not active after masking
1 = ssi_rxf_intr interrupt is full after masking
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
3 rxois
Receive FIFO Overflow Interrupt Status
0 = ssi_rxo_intr interrupt is not active after masking
1 = ssi_rxo_intr interrupt is active after masking
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
2 rxuis
Receive FIFO Underflow Interrupt Status
0 = ssi_rxu_intr interrupt is not active after masking
1 = ssi_rxu_intr interrupt is active after masking
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
1 txois
Transmit FIFO Overflow Interrupt Status
0 = ssi_txo_intr interrupt is not active after masking
1 = ssi_txo_intr interrupt is active after masking
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0
0 txeis
Transmit FIFO Empty Interrupt Status
0 = ssi_txe_intr interrupt is not active after masking
1 = ssi_txe_intr interrupt is active after masking
Value Description
0x0 INACTIVE
0x1 ACTIVE
RO 0x0