imr
Interrupt Mask Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_spim_0_spim | 0xFFDA4000 | 0xFFDA402C |
| i_spim_1_spim | 0xFFDA5000 | 0xFFDA502C |
Offset: 0x2C
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
mstim RW 0x1 |
rxfim RW 0x1 |
rxoim RW 0x1 |
rxuim RW 0x1 |
txoim RW 0x1 |
txeim RW 0x1 |
|||||||||
imr Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 5 | mstim | Multi-Master Contention Interrupt Mask. This bit field is not present if the DW_apb_ssi is configured as a serial-slave device. 0 - ssi_mst_intr interrupt is masked 1 - ssi_mst_intr interrupt is not masked |
RW | 0x1 | ||||||
| 4 | rxfim | Receive FIFO Full Interrupt Mask 0 - ssi_rxf_intr interrupt is masked 1 - ssi_rxf_intr interrupt is not masked
|
RW | 0x1 | ||||||
| 3 | rxoim | Receive FIFO Overflow Interrupt Mask 0 - ssi_rxo_intr interrupt is masked 1 - ssi_rxo_intr interrupt is not masked
|
RW | 0x1 | ||||||
| 2 | rxuim | Receive FIFO Underflow Interrupt Mask 0 - ssi_rxu_intr interrupt is masked 1 - ssi_rxu_intr interrupt is not masked
|
RW | 0x1 | ||||||
| 1 | txoim | Transmit FIFO Overflow Interrupt Mask 0 - ssi_txo_intr interrupt is masked 1 - ssi_txo_intr interrupt is not masked
|
RW | 0x1 | ||||||
| 0 | txeim | Transmit FIFO Empty Interrupt Mask 0 - ssi_txe_intr interrupt is masked 1 - ssi_txe_intr interrupt is not masked
|
RW | 0x1 |