sr
This register is used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. The status register may be read at any time. None of the bits in this register request an interrupt.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_spim_0_spim | 0xFFDA4000 | 0xFFDA4028 |
| i_spim_1_spim | 0xFFDA5000 | 0xFFDA5028 |
Offset: 0x28
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
dcol RO 0x0 |
Reserved |
rff RO 0x0 |
rfne RO 0x0 |
tfe RO 0x1 |
tfnf RO 0x1 |
busy RO 0x0 |
||||||||
sr Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 6 | dcol | Relevant only when the DW_apb_ssi is configured as a master device. This bit is set if the DW_apb_ssi master is actively transmitting when another master selects this device as a slave. This informs the processor that the last data transfer was halted before completion. This bit is cleared when read.
|
RO | 0x0 | ||||||
| 4 | rff | Reports receive FIFO condition.
|
RO | 0x0 | ||||||
| 3 | rfne | Reports receive FIFO condition.
|
RO | 0x0 | ||||||
| 2 | tfe | Reports transmit FIFO condition.
|
RO | 0x1 | ||||||
| 1 | tfnf | Reports transmit FIFO condition.
|
RO | 0x1 | ||||||
| 0 | busy | Reports the staus of a serial transfer
|
RO | 0x0 |