rxflr

         Receive FIFO Level Register
      
Module Instance Base Address Register Address
i_spim_0_spim 0xFFDA4000 0xFFDA4024
i_spim_1_spim 0xFFDA5000 0xFFDA5024

Offset: 0x24

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

rxtfl

RO 0x0

rxflr Fields

Bit Name Description Access Reset
8:0 rxtfl
Receive FIFO Level.
Contains the number of valid data entries in the receive FIFO.
RO 0x0