rxftlr

         Receive FIFO Threshold level.
This register controls the threshold value for the receive FIFO memory.
The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.

Module Instance	Base Address	Register Address
`i_spim_0_spim`	`0xFFDA4000`	`0xFFDA401C`
`i_spim_1_spim`	`0xFFDA5000`	`0xFFDA501C`

Offset: 0x1C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`rft` `RW 0x0`

rxftlr Fields

Bit	Name	Description	Access	Reset
7:0	`rft`	Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256. This register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than the depth of the FIFO, this field is not written and retains its current value. When the number of receive FIFO entries is greater than or equal to this value + 1, the receive FIFO full interrupt is triggered.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

7:0

rft

Receive FIFO Threshold.
Controls the level of entries (or above) at which the receive FIFO
controller triggers an interrupt. The FIFO depth is configurable in
the range 2-256. This register is sized to the number of address bits
needed to access the FIFO. If you attempt to set this value greater
than the depth of the FIFO, this field is not written and retains its
current value. When the number of receive FIFO entries is greater than
or equal to this value + 1, the receive FIFO full interrupt is triggered.

RW

0x0