noc_mpu_fpga2soc_axi128_I_main_QosGenerator Address Map

Module Instance Base Address End Address
i_noc_mpu_m0_fpga2soc_axi128_I_main_QosGenerator 0xFFD16200 0xFFD1627F
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
fpga2soc_axi128_I_main_QosGenerator_Id_CoreId 0x0 32 RO 0xDC0D0004

fpga2soc_axi128_I_main_QosGenerator_Id_RevisionId 0x4 32 RO 0x129FF00

fpga2soc_axi128_I_main_QosGenerator_Priority 0x8 32 RW 0x80000202
Priority register.
fpga2soc_axi128_I_main_QosGenerator_Mode 0xC 32 RW 0x1

fpga2soc_axi128_I_main_QosGenerator_Bandwidth 0x10 32 RW 0xC80

fpga2soc_axi128_I_main_QosGenerator_Saturation 0x14 32 RW 0x8

fpga2soc_axi128_I_main_QosGenerator_ExtControl 0x18 32 RW 0x0
External inputs control.