noc_fw_ddr_mpu_fpga2sdram_ddr_scr Address Map

Module Instance Base Address End Address
noc_fw_ddr_mpu_fpga2sdram_ddr_scr 0xFFD13300 0xFFD133FF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
enable 0x0 32 RW 0x0 
Enable
enable_set 0x4 32 WO 0x0 
Sets Master Region Enable field when written with 1
enable_clear 0x8 32 WO 0x0 
Clears Master Region Enable field when written with 1
mpuregion0addr 0x10 32 RW 0x0 
Base and Limit definition for MPU Region 0
mpuregion1addr 0x14 32 RW 0x0 
Base and Limit definition for MPU Region 1
mpuregion2addr 0x18 32 RW 0x0 
Base and Limit definition for MPU Region 2
mpuregion3addr 0x1C 32 RW 0x0 
Base and Limit definition for MPU Region 3
fpga2sdram0region0addr 0x20 32 RW 0x0 
Base and Limit definition for FPGA2SDRAM0 Region 0
fpga2sdram0region1addr 0x24 32 RW 0x0 
Base and Limit definition for FPGA2SDRAM0 Region 1
fpga2sdram0region2addr 0x28 32 RW 0x0 
Base and Limit definition for FPGA2SDRAM0 Region 2
fpga2sdram0region3addr 0x2C 32 RW 0x0 
Base and Limit definition for FPGA2SDRAM0 Region 3
fpga2sdram1region0addr 0x30 32 RW 0x0 
Base and Limit definition for FPGA2SDRAM1 Region 0
fpga2sdram1region1addr 0x34 32 RW 0x0 
Base and Limit definition for FPGA2SDRAM1 Region 1
fpga2sdram1region2addr 0x38 32 RW 0x0 
Base and Limit definition for FPGA2SDRAM1 Region 2
fpga2sdram1region3addr 0x3C 32 RW 0x0 
Base and Limit definition for FPGA2SDRAM1 Region 3
fpga2sdram2region0addr 0x40 32 RW 0x0 
Base and Limit definition for FPGA2SDRAM2 Region 0
fpga2sdram2region1addr 0x44 32 RW 0x0 
Base and Limit definition for FPGA2SDRAM2 Region 1
fpga2sdram2region2addr 0x48 32 RW 0x0 
Base and Limit definition for FPGA2SDRAM2 Region 2
fpga2sdram2region3addr 0x4C 32 RW 0x0 
Base and Limit definition for FPGA2SDRAM2 Region 3