noc_mpu_m0_ddr_T_main_Probe Address Map

Module Instance	Base Address	End Address
`i_noc_mpu_m0_ddr_T_main_Probe`	`0xFFD12000`	`0xFFD123FF`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value	Description
`ddr_T_main_Probe_Id_CoreId`	`0x0`	`32`	`RO`	`0xFA9ECC06`
`ddr_T_main_Probe_Id_RevisionId`	`0x4`	`32`	`RO`	`0x129FF00`
`ddr_T_main_Probe_MainCtl`	`0x8`	`32`	`RW`	`0x0`	Register MainCtl contains probe global control bits. The register has seven bit fields:
`ddr_T_main_Probe_CfgCtl`	`0xC`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_FilterLut`	`0x14`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_TraceAlarmEn`	`0x18`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_TraceAlarmStatus`	`0x1C`	`32`	`RO`	`0x0`
`ddr_T_main_Probe_TraceAlarmClr`	`0x20`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_StatPeriod`	`0x24`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_StatGo`	`0x28`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_StatAlarmMin`	`0x2C`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_StatAlarmMax`	`0x30`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_StatAlarmStatus`	`0x34`	`32`	`RO`	`0x0`
`ddr_T_main_Probe_StatAlarmClr`	`0x38`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_StatAlarmEn`	`0x3C`	`32`	`RW`	`0x1`
`ddr_T_main_Probe_Filters_0_RouteIdBase`	`0x44`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_0_RouteIdMask`	`0x48`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_0_AddrBase_Low`	`0x4C`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_0_WindowSize`	`0x54`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_0_SecurityBase`	`0x58`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_0_SecurityMask`	`0x5C`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_0_Opcode`	`0x60`	`32`	`RW`	`0x0`	Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):
`ddr_T_main_Probe_Filters_0_Status`	`0x64`	`32`	`RW`	`0x0`	Register Status is 2-bit register that selects candidate packets based on packet status.
`ddr_T_main_Probe_Filters_0_Length`	`0x68`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_0_Urgency`	`0x6C`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_1_RouteIdBase`	`0x80`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_1_RouteIdMask`	`0x84`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_1_AddrBase_Low`	`0x88`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_1_WindowSize`	`0x90`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_1_SecurityBase`	`0x94`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_1_SecurityMask`	`0x98`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_1_Opcode`	`0x9C`	`32`	`RW`	`0x0`	Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):
`ddr_T_main_Probe_Filters_1_Status`	`0xA0`	`32`	`RW`	`0x0`	Register Status is 2-bit register that selects candidate packets based on packet status.
`ddr_T_main_Probe_Filters_1_Length`	`0xA4`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_1_Urgency`	`0xA8`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_2_RouteIdBase`	`0xBC`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_2_RouteIdMask`	`0xC0`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_2_AddrBase_Low`	`0xC4`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_2_WindowSize`	`0xCC`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_2_SecurityBase`	`0xD0`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_2_SecurityMask`	`0xD4`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_2_Opcode`	`0xD8`	`32`	`RW`	`0x0`	Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):
`ddr_T_main_Probe_Filters_2_Status`	`0xDC`	`32`	`RW`	`0x0`	Register Status is 2-bit register that selects candidate packets based on packet status.
`ddr_T_main_Probe_Filters_2_Length`	`0xE0`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_2_Urgency`	`0xE4`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_3_RouteIdBase`	`0xF8`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_3_RouteIdMask`	`0xFC`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_3_AddrBase_Low`	`0x100`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_3_WindowSize`	`0x108`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_3_SecurityBase`	`0x10C`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_3_SecurityMask`	`0x110`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_3_Opcode`	`0x114`	`32`	`RW`	`0x0`	Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):
`ddr_T_main_Probe_Filters_3_Status`	`0x118`	`32`	`RW`	`0x0`	Register Status is 2-bit register that selects candidate packets based on packet status.
`ddr_T_main_Probe_Filters_3_Length`	`0x11C`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Filters_3_Urgency`	`0x120`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Counters_0_Src`	`0x138`	`32`	`RW`	`0x0`	Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index, or unimplemented Filter) are equivalent to OFF.
`ddr_T_main_Probe_Counters_0_AlarmMode`	`0x13C`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Counters_0_Val`	`0x140`	`32`	`RO`	`0x0`
`ddr_T_main_Probe_Counters_1_Src`	`0x14C`	`32`	`RW`	`0x0`	Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index, or unimplemented Filter) are equivalent to OFF.
`ddr_T_main_Probe_Counters_1_AlarmMode`	`0x150`	`32`	`RW`	`0x0`
`ddr_T_main_Probe_Counters_1_Val`	`0x154`	`32`	`RO`	`0x0`