noc_mpu_m0_fpga2soc_rate_ad_main_RateAdapter Address Map

Module Instance	Base Address	End Address
`i_noc_mpu_m0_fpga2soc_rate_ad_main_RateAdapter`	`0xFFD11400`	`0xFFD114FF`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value
`fpga2soc_rate_ad_main_RateAdapter_Id_CoreId`	`0x0`	`32`	`RO`	`0x88DEAF01`
`fpga2soc_rate_ad_main_RateAdapter_Id_RevisionId`	`0x4`	`32`	`RO`	`0x129FF00`
`fpga2soc_rate_ad_main_RateAdapter_Rate`	`0x8`	`32`	`RW`	`0x0`
`fpga2soc_rate_ad_main_RateAdapter_Bypass`	`0xC`	`32`	`RW`	`0x0`