noc_mpu_m0_fpga2soc_rate_ad_main_RateAdapter Summary

Base Address: 0xFFD11400

Register Address Offset	Bit Fields
`i_noc_mpu_m0_fpga2soc_rate_ad_main_RateAdapter`
`fpga2soc_rate_ad_main_RateAdapter_Id_CoreId` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`CORECHECKSUM` `RO 0x88DEAF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`CORECHECKSUM` `RO 0x88DEAF`								`CORETYPEID` `RO 0x1`
`fpga2soc_rate_ad_main_RateAdapter_Id_RevisionId` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`FLEXNOCID` `RO 0x129FF`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`FLEXNOCID` `RO 0x129FF`								`USERID` `RO 0x0`
`fpga2soc_rate_ad_main_RateAdapter_Rate` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`						`RATE` `RW 0x0`
`fpga2soc_rate_ad_main_RateAdapter_Bypass` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`BYPASS` `RW 0x0`