noc_timeout

Module Instance	Base Address	Register Address
`i_sys_mgr_core`	`0xFFD06000`	`0xFFD060C0`

Offset: 0xC0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`en` `0x0`

noc_timeout Fields

Bit	Name	Description	Access	Reset
0	`en`	NOC Timeout Enable. You can set this bit to enable an automatic timeout that flushes all pending transactions in the HPS-to-FPGA and lightweight HPS-to-FPGA bridges when they are shutdown and reset. To use this automatic timeout, the bridges must be operating above 100 MHz. The automatic timeout duration is approximately 320 ns. If your system application handles and completes all transactions before shutting down the bridges, this bit does not need to be enabled.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

en

NOC Timeout Enable. You can set this bit to enable an automatic timeout that flushes all pending transactions in the HPS-to-FPGA and lightweight HPS-to-FPGA bridges when they are shutdown and reset.  
To use this automatic timeout, the bridges must be operating above 100 MHz.  The automatic timeout duration is approximately 320 ns.  
If your system application handles and completes all transactions before shutting down the bridges, this bit does not need to be enabled.

RW

0x0