mpu_clear_l1_parity

         Parity status clear bit.
A write to 1 of a specific bit clears the curresponding parity status bit.
A read of this register should not return an error, but the actual read value is undefined.

[17] CPU1 SCU parity error
[16] CPU0 SCU parity error

[15] CPU1 BTAC parity error
[14] CPU1 GHB parity error
[13] CPU1 instruction tag RAM parity error
[12] CPU1 instruction data RAM parity error
[11] CPU1 main TLB parity error
[10] CPU1 data outer RAM parity error
[9]  CPU1 data tag RAM parity error
[8]  CPU1 data data RAM parity error.

[7]  CPU0 BTAC parity error
[6]  CPU0 GHB parity error
[5]  CPU0 instruction tag RAM parity error
[4]  CPU0 instruction data RAM parity error
[3]  CPU0 main TLB parity error
[2]  CPU0 data outer RAM parity error
[1]  CPU0 data tag RAM parity error
[0]  CPU0 data data RAM parity error.


      
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD06000 0xFFD060B0

Offset: 0xB0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

scu

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

cpu1

0x0

cpu0

0x0

mpu_clear_l1_parity Fields

Bit Name Description Access Reset
17:16 scu
SCU parity interrupt clear. Write 1 to Clear
RW 0x0
15:8 cpu1
CPU1 L1 parity interrupt clear. Write 1 to Clear
RW 0x0
7:0 cpu0
CPU0 L1 parity interrupt clear. Write 1 to Clear
RW 0x0