mpu_status_l2_ecc

         This is a read only register which reads the current mpu L2 ecc interrupt status.
A write to this register should return an error.
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD06000 0xFFD060A4

Offset: 0xA4

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

merr_pending

0x0

Reserved

merr_info

0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

serr_pending

0x0

Reserved

serr_info

0x0

mpu_status_l2_ecc Fields

Bit Name Description Access Reset
31 merr_pending 
Unmaksed value of a pending multiple bits ECC error status.
 RO 0x0
27:16 merr_info 
12 bit Serr Info field. 
In Baum this will be the index and way information where the ECC error occured.
 RO 0x0
15 serr_pending 
Unmaksed value of a pending single bit ECC error status.
 RO 0x0
11:0 serr_info 
12 bit Serr Info field. 
In Baum this will be the index and way information where the ECC error occured.
 RO 0x0