ecc_intmask_clr

         Write 1 to Clear a specific modules interrupt mask.
Reads should not return an error, but the actual read value is "Undefined" .

      
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD06000 0xFFD06098

Offset: 0x98

Access: WO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

ddr1

0x0

ddr0

0x0

sdmmcb

0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

sdmmca

0x0

qspi

0x0

nand_rd

0x0

nand_wr

0x0

nand_buf

0x0

dma

0x0

emac2_tx

0x0

emac2_rx

0x0

emac1_tx

0x0

emac1_rx

0x0

emac0_tx

0x0

emac0_rx

0x0

usb1

0x0

usb0

0x0

ocram

0x0

l2

0x0

ecc_intmask_clr Fields

Bit Name Description Access Reset
18 ddr1

WO 0x0
17 ddr0

WO 0x0
16 sdmmcb

WO 0x0
15 sdmmca

WO 0x0
14 qspi

WO 0x0
13 nand_rd

WO 0x0
12 nand_wr

WO 0x0
11 nand_buf

WO 0x0
10 dma

WO 0x0
9 emac2_tx

WO 0x0
8 emac2_rx

WO 0x0
7 emac1_tx

WO 0x0
6 emac1_rx

WO 0x0
5 emac0_tx

WO 0x0
4 emac0_rx

WO 0x0
3 usb1

WO 0x0
2 usb0

WO 0x0
1 ocram

WO 0x0
0 l2

WO 0x0