dma

         Registers used by the DMA Controller. All fields are reset by a cold or warm reset.
These register bits should be updated during system initialization prior to removing the DMA controller from reset. They may not be changed dynamically during DMA operation.
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD06000 0xFFD06020

Offset: 0x20

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

irq_ns

RW 0x0

Reserved

mgr_ns

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

chansel_2

RW 0x1

Reserved

chansel_1

RW 0x0

Reserved

chansel_0

RW 0x0

dma Fields

Bit Name Description Access Reset
31:24 irq_ns 
Specifies the security state of an event-interrupt resource.
If bit index [x] is 0, the DMAC assigns event<x> or irq[x] to the Secure state.
If bit index [x] is 1, the DMAC assigns event<x> or irq[x] to the Non-secure state.
RW 0x0
16 mgr_ns 
Specifies the security state of the DMA manager thread.
0 = assigns DMA manager to the Secure state.
1 = assigns DMA manager to the Non-secure state.
Sampled by the DMA controller when it exits from reset.
RW 0x0
8 chansel_2 
select between FPGA interface 5 and Security Manager to be mapped to DMA peripheral request index 5
Value Description
0 FPGA
1 SECMGR
RW 0x1
4 chansel_1 
select between FPGA interface 7 and I2C4_Rx to be mapped to DMA peripheral request index 7
Value Description
0 FPGA
1 I2C4_RX
RW 0x0
0 chansel_0 
Select between FPGA interface 6 and I2C4_Tx to be mapped to DMA peripheral request index 6
Value Description
0 FPGA
1 I2C4_TX
RW 0x0