mpu_ctrl_l2_ecc

         This register is used to enable ECC on the L2 Data RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error.
Some fileds of this register are only reset by a cold reset (ignores warm reset).
Some fields are affected by both warm and cold reset.
Module Instance Base Address Register Address
i_sys_mgr_core 0xFFD06000 0xFFD06010

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

inj_type

RW 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

inj_en

RW 0x0

Reserved

ecc_en

RW 0x0

mpu_ctrl_l2_ecc Fields

Bit Name Description Access Reset
16 inj_type 
MPU L2 ECC error injection type. This bit will get reset on a warm reset and cold reset.
Value Description
0 single_bit
1 double_bit
RW 0x0
8 inj_en 
Error injection enable. Write 1 here to enable error injection to MPU L2.
Please note that if ECC is not enabled by writing 1 to ecc_en bit there wont be any error injections.

This bit will get reset on a warm reset and cold reset.
RW 0x0
0 ecc_en 
Enable Single bit or Double bit error Detection and Single bit Error Correction  for L2 Data RAM
Only reset by a cold reset (ignores warm reset).
RW 0x0